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f C = =
MICRF500
When FSK modulation is applied to the VCO the PLL is using
the dividers A1, N1 and M1. When Mod1 = 1 and Mod0 = 0
it is possible to switch between the different dividers in the
PLL. DATAIXO controls the switching. When DATAIXO = 0
the PLL uses dividers A0, N0 and M0. When DATAIXO = 1 the
PLL uses dividers A1, N1 and M1. Switching between the
different dividers can be used to implement FSK modulation.
The N, M and A values can be calculated from the formula:
f XCO f RF
M 64 × N + A
where f C is the comparison frequency.
The 80bit control word is first read into a shift-register, and is
then loaded into a parallel register by a transition of the
Micrel
6. A new control word is entered into the first register. A
transition on the REGIN signal when CLKIN is high will
now turn the power amplifier off.
7. When the power amplifier is turned off an internal load
pulse is generated. The new control word is loaded into
the parallel register and the circuit enters a new mode
(in this case power down mode). CLKIN must go low
after the internal load pulse is generated.
As long as transitions on REGIN are avoided when CLKIN is
high, a new control word can be clocked into the first register
any time without affecting the operation of the transceiver.
Example 1. f RF = 869.0MHz, frequency deviation: ≈ ± 10kHz,
f XCO = 10.00MHz. FSK modulation is implemented by switch-
ing between dividers.
REGIN signal (positive or negative) when the CLKIN signal is
high. The circuit then goes directly into the specified mode
(receive, transmit, etc.).
Tx
A1
9
A0
27
N1
137
N0
134
M1
101
M0
99
1
23
4
5
6
7
Rx
50
50
135
135
100
100
RxFilt
Pa2
Pa1
Pa0
Gc
ByLNA
CLKIN
REGIN
LOAD_INT
Tx
Rx
Tx
Rx
0
0
Ref6
0
0
1
1
Ref5
0
0
1
1
Ref4
0
0
1
1
Ref3
0
0
1
1
Ref2
0
0
0
0
Ref1
0
0
PA_C
Ref0
Cpmp1 Cpmp0
Fc1
Fc0
OutS2
LOCKDET
Tx
0
1
0
0
1
0
Figure 10. Timing of CLKIN, REGIN and the Internal
LOAD_INT and PA_C Signals
Rx
0
OutS1
1
OutS0
0
Mod1
0
Mod0
1
RT
0
Pu
1. The second last bit is clocked into the first shift register
( ‘ 1 ’ ).
Tx
Rx
0
0
0
0
1
1
0
0
1
0
1
1
2. The last bit is clocked into the first shift register ( ‘ 1 ’ ).
3. A transition on the REGIN signal generates an internal
load pulse that loads the control word into the parallel
register. The circuit enters the new mode (in this case
Tx-mode). The circuit stabilizes in the new mode.
4. When the clock signal goes low, the power amplifier
(PA) is turned on slowly in order to minimize spurious
components on the RF output signal. To be sure the
PLL is in lock before the PA is turned on, the PA should
be turned on after LOCKDET has been set.
The negative transition on the clock signal should come
a minimum time of one period of the comparison fre-
quency after the internal load pulse is generated.
5. The power amplifier is fully turned on.
Binary form: (MSB to the left):
Tx: 001001 011011 000010001001
000010000110 0001100101 0001100011
011110000000001010001011
Rx: 110010 110010 000010000111
000010000111 0001100100 0001100100
01011110000000001010001001
When FSK modulation is implemented by switching between
the different dividers A, N and M values corresponding to the
receive frequency and both transmit frequencies have to be
found.
MICRF500
16
March 2003
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